2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

发布时间:2020-06-08 08:20:13 浏览次数:289 作者:oumao18 来源:嘉泰姆
摘要:CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度
2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

目录Iej嘉泰姆

1.产品概述                       2.产品特点Iej嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 Iej嘉泰姆
5.产品封装图                     6.电路原理图                   Iej嘉泰姆
7.功能概述                        8.相关产品Iej嘉泰姆

一,产品概述(General Description)         Iej嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.Iej嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.Iej嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withIej嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slewIej嘉泰姆
rate. All inputs and outputs are rail-to-rail.Iej嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).Iej嘉泰姆
二.产品特点(Features)Iej嘉泰姆


· 2.6V to 6.5V Input Supply Range Iej嘉泰姆

· Current-Mode Step-Up Regulator Iej嘉泰姆

 - Fast Transient Response Iej嘉泰姆

 - 1.2MHz Fixed Operating Frequency Iej嘉泰姆

· ±1.5% High-Accuracy Output Voltage Iej嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET Iej嘉泰姆

· High Efficiency Iej嘉泰姆

· Low Quiescent Current (0.6mA Typical) Iej嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF Iej嘉泰姆

· High-performance Operational Amplifiers Iej嘉泰姆

 - ±150mA Output Short-Circuit CurrentIej嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth Iej嘉泰姆

 - Rail-to-Rail Inputs/Outputs Iej嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs Iej嘉泰姆

· Over-Temperature Protection Iej嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) Iej嘉泰姆

· Lead Free Available (RoHS Compliant)Iej嘉泰姆

三,应用范围 (Applications)Iej嘉泰姆


    TFT LCD Displays for MonitorsIej嘉泰姆
   TFT LCD Displays for Notebook ComputersIej嘉泰姆
   Automotive DisplaysIej嘉泰姆
四.下载产品资料PDF文档 Iej嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持Iej嘉泰姆

 QQ截图20160419174301.jpgIej嘉泰姆

五,产品封装图 (Package)Iej嘉泰姆


blob.pngIej嘉泰姆
blob.pngPin Function DescriptionIej嘉泰姆

PinIej嘉泰姆

NameIej嘉泰姆

Function DescriptionIej嘉泰姆

CXSU63137Iej嘉泰姆

CXSU63137-1Iej嘉泰姆

CXSU63137-2Iej嘉泰姆

1Iej嘉泰姆

SRCIej嘉泰姆

SRCIej嘉泰姆

SRCIej嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. BypassIej嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.Iej嘉泰姆

2Iej嘉泰姆

REFIej嘉泰姆

REFIej嘉泰姆

REFIej嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofIej嘉泰姆
0.22μFcapacitor closed to the pins.Iej嘉泰姆

3Iej嘉泰姆

AGNDIej嘉泰姆

AGNDIej嘉泰姆

AGNDIej嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect toIej嘉泰姆
power ground (PGND) underneath the IC.Iej嘉泰姆

4Iej嘉泰姆

PGNDIej嘉泰姆

PGNDIej嘉泰姆

PGNDIej嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-upIej嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputIej嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog groundIej嘉泰姆
(AGND) underneath the IC.Iej嘉泰姆

5Iej嘉泰姆

OUT1Iej嘉泰姆

OUT1Iej嘉泰姆

OUT1Iej嘉泰姆

Output of Operational-Amplifier 1Iej嘉泰姆

6Iej嘉泰姆

NEG1Iej嘉泰姆

NEG1Iej嘉泰姆

NEG1Iej嘉泰姆

Inverting Input of Operational-Amplifier 1Iej嘉泰姆

7Iej嘉泰姆

POS1Iej嘉泰姆

POS1Iej嘉泰姆

POS1Iej嘉泰姆

Non-inverting Input of Operational-Amplifier 1Iej嘉泰姆

8Iej嘉泰姆

NCIej嘉泰姆

OUT2Iej嘉泰姆

OUT2Iej嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalIej嘉泰姆
connected of CXSU63137.Iej嘉泰姆

9Iej嘉泰姆

NCIej嘉泰姆

NEG2Iej嘉泰姆

NEG2Iej嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalIej嘉泰姆
connected of CXSU63137.Iej嘉泰姆

10Iej嘉泰姆

ICIej嘉泰姆

POS2Iej嘉泰姆

POS2Iej嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. InternalIej嘉泰姆
connected to GND of CXSU63137Iej嘉泰姆

11Iej嘉泰姆

BGNDIej嘉泰姆

BGNDIej嘉泰姆

BGNDIej嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)Iej嘉泰姆
underneath the IC.Iej嘉泰姆

12Iej嘉泰姆

NCIej嘉泰姆

NCIej嘉泰姆

POS3Iej嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internalIej嘉泰姆
connected of CXSU63137/CXSU63137.Iej嘉泰姆

13Iej嘉泰姆

NCIej嘉泰姆

NCIej嘉泰姆

OUT3Iej嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.Iej嘉泰姆

14Iej嘉泰姆

SUPIej嘉泰姆

SUPIej嘉泰姆

SUPIej嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. BypassIej嘉泰姆
SUP to BGND with a 0.1μF capacitor.Iej嘉泰姆

15Iej嘉泰姆

NCIej嘉泰姆

POS3Iej嘉泰姆

POS4Iej嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertingIej嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.Iej嘉泰姆

16Iej嘉泰姆

NCIej嘉泰姆

NEG3Iej嘉泰姆

NEG4Iej嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofIej嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.Iej嘉泰姆

17Iej嘉泰姆

NCIej嘉泰姆

OUT3Iej嘉泰姆

OUT4Iej嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofIej嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.Iej嘉泰姆

18Iej嘉泰姆

ICIej嘉泰姆

ICIej嘉泰姆

POS5Iej嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connectedIej嘉泰姆
to GND of CXSU63137/CXSU63137.Iej嘉泰姆

19Iej嘉泰姆

NCIej嘉泰姆

NCIej嘉泰姆

NEG5Iej嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connectedIej嘉泰姆
of CXSU63137/CXSU63137.Iej嘉泰姆

20Iej嘉泰姆

NCIej嘉泰姆

NCIej嘉泰姆

OUT5Iej嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.Iej嘉泰姆

21Iej嘉泰姆

LXIej嘉泰姆

LXIej嘉泰姆

LXIej嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductorIej嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.Iej嘉泰姆

22Iej嘉泰姆

INIej嘉泰姆

INIej嘉泰姆

INIej嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can rangeIej嘉泰姆
from 2.6V to 6.5V.Iej嘉泰姆

23Iej嘉泰姆

FBIej嘉泰姆

FBIej嘉泰姆

FBIej嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider fromIej嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withinIej嘉泰姆
5mm of FB.Iej嘉泰姆

24Iej嘉泰姆

COMPIej嘉泰姆

COMPIej嘉泰姆

COMPIej嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCIej嘉泰姆
from COMP to AGND.Iej嘉泰姆

PinFunction DescriptionIej嘉泰姆

PinIej嘉泰姆

NameIej嘉泰姆

Function DescriptionIej嘉泰姆

CXSU63137Iej嘉泰姆

CXSU63137-1Iej嘉泰姆

CXSU63137-2Iej嘉泰姆

24Iej嘉泰姆

COMPIej嘉泰姆

COMPIej嘉泰姆

COMPIej嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCIej嘉泰姆
from COMP to AGND.Iej嘉泰姆

25Iej嘉泰姆

FBPIej嘉泰姆

FBPIej嘉泰姆

FBPIej嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of aIej嘉泰姆
resistive voltage-divider between the regulator output and AGND to set theIej嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-dividerIej嘉泰姆
close to the pin.Iej嘉泰姆

26Iej嘉泰姆

DRVPIej嘉泰姆

DRVPIej嘉泰姆

DRVPIej嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channelIej嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.Iej嘉泰姆

27Iej嘉泰姆

FBNIej嘉泰姆

FBNIej嘉泰姆

FBNIej嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of aIej嘉泰姆
resistive voltage-divider between the regulator output and REF to set theIej嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-dividerIej嘉泰姆
close to the pin.Iej嘉泰姆

28Iej嘉泰姆

DRVNIej嘉泰姆

DRVNIej嘉泰姆

DRVNIej嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channelIej嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.Iej嘉泰姆

29Iej嘉泰姆

DELIej嘉泰姆

DELIej嘉泰姆

DELIej嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND toIej嘉泰姆
set the high-voltage switch startup delay.Iej嘉泰姆

30Iej嘉泰姆

CTLIej嘉泰姆

CTLIej嘉泰姆

CTLIej嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchIej嘉泰姆
between COM and SRC is on and the high-voltage switch between COM andIej嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRCIej嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL isIej嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thanIej嘉泰姆
1.25V.Iej嘉泰姆

31Iej嘉泰姆

DRNIej嘉泰姆

DRNIej嘉泰姆

DRNIej嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channelIej嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceedIej嘉泰姆
VSRC.Iej嘉泰姆

32Iej嘉泰姆

COMIej嘉泰姆

COMIej嘉泰姆

COMIej嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow theIej嘉泰姆
voltage on COM to exceed VSRC.Iej嘉泰姆

六.电路原理图Iej嘉泰姆
七,功能概述Iej嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:Iej嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.Iej嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.Iej嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.Iej嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.Iej嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.Iej嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.Iej嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-upIej嘉泰姆
八,相关产品Iej嘉泰姆

Switching Regulator > Boost ConverterIej嘉泰姆

 Part_No Iej嘉泰姆

PackageIej嘉泰姆

Archi-tecture Iej嘉泰姆

Input Iej嘉泰姆

Voltage    Iej嘉泰姆

Max Adj.Iej嘉泰姆

Output Iej嘉泰姆

Voltage Iej嘉泰姆

Switch Current Limit (max) Iej嘉泰姆

Fixed Iej嘉泰姆

Output Iej嘉泰姆

Voltage  Iej嘉泰姆

Switching Iej嘉泰姆

Frequency Iej嘉泰姆

Internal Power   Switch Iej嘉泰姆

Sync. Rectifier Iej嘉泰姆

 

minIej嘉泰姆

maxIej嘉泰姆

minIej嘉泰姆

maxIej嘉泰姆

(A)Iej嘉泰姆

(V)Iej嘉泰姆

(kHz)Iej嘉泰姆

 

CXSU63133Iej嘉泰姆

SOT89Iej嘉泰姆

VM Iej嘉泰姆

0.9Iej嘉泰姆

5.5Iej嘉泰姆

2.5Iej嘉泰姆

5.5Iej嘉泰姆

0.5Iej嘉泰姆

1.8|2.6|2.8|3Iej嘉泰姆

|3.3|3.8|4.5|5Iej嘉泰姆

-Iej嘉泰姆

NoIej嘉泰姆

YesIej嘉泰姆

CXSU63134Iej嘉泰姆

MSOP8|TSSOP8Iej嘉泰姆

|SOP8Iej嘉泰姆

VMIej嘉泰姆

2.5Iej嘉泰姆

5.5Iej嘉泰姆

2.5Iej嘉泰姆

-Iej嘉泰姆

-Iej嘉泰姆

-Iej嘉泰姆

200 ~ 1000Iej嘉泰姆

NoIej嘉泰姆

NoIej嘉泰姆

CXSU63135Iej嘉泰姆

TSSOP8|SOP-8PIej嘉泰姆

VMIej嘉泰姆

1Iej嘉泰姆

5.5Iej嘉泰姆

2.5Iej嘉泰姆

5Iej嘉泰姆

1Iej嘉泰姆

2.5|3.3Iej嘉泰姆

300Iej嘉泰姆

YesIej嘉泰姆

YesIej嘉泰姆

CXSU63136Iej嘉泰姆

SOP8Iej嘉泰姆

CMIej嘉泰姆

3Iej嘉泰姆

40Iej嘉泰姆

1.25Iej嘉泰姆

40Iej嘉泰姆

1.5Iej嘉泰姆

-Iej嘉泰姆

33 ~ 100Iej嘉泰姆

YesIej嘉泰姆

NoIej嘉泰姆

CXSU63137Iej嘉泰姆

TQFN5x5-32Iej嘉泰姆

CMIej嘉泰姆

2.5Iej嘉泰姆

6.5Iej嘉泰姆

2.5Iej嘉泰姆

18Iej嘉泰姆

3Iej嘉泰姆

NoIej嘉泰姆

1200Iej嘉泰姆

YesIej嘉泰姆

NoIej嘉泰姆

CXSU63138Iej嘉泰姆

TSOT23-5Iej嘉泰姆

TDFN2x2-6Iej嘉泰姆

CMIej嘉泰姆

2.5Iej嘉泰姆

6Iej嘉泰姆

2.5Iej嘉泰姆

20Iej嘉泰姆

2Iej嘉泰姆

-Iej嘉泰姆

1500Iej嘉泰姆

YesIej嘉泰姆

NoIej嘉泰姆

CXSU63139Iej嘉泰姆

TQFN4x4-6Iej嘉泰姆

TDFN3x3-12Iej嘉泰姆

CMIej嘉泰姆

1.8Iej嘉泰姆

5.5Iej嘉泰姆

2.7Iej嘉泰姆

5.5Iej嘉泰姆

5Iej嘉泰姆

-Iej嘉泰姆

1.2Iej嘉泰姆

YesIej嘉泰姆

YesIej嘉泰姆

CXSU63140Iej嘉泰姆

SOT23-5Iej嘉泰姆

CMIej嘉泰姆

2.5Iej嘉泰姆

6Iej嘉泰姆

2.5Iej嘉泰姆

32Iej嘉泰姆

1Iej嘉泰姆

-Iej嘉泰姆

1000Iej嘉泰姆

YesIej嘉泰姆

NoIej嘉泰姆

CXSU63141Iej嘉泰姆

TSOT-23-6 Iej嘉泰姆

TDFN2x2-8Iej嘉泰姆

CMIej嘉泰姆

1.2Iej嘉泰姆

5.5Iej嘉泰姆

1.8Iej嘉泰姆

5.5Iej嘉泰姆

1.2Iej嘉泰姆

-Iej嘉泰姆

1.2Iej嘉泰姆

YesIej嘉泰姆

YesIej嘉泰姆

 Iej嘉泰姆

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