目录nV2嘉泰姆

1.产品概述                       2.产品特点nV2嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 nV2嘉泰姆
5.产品封装图                     6.电路原理图                   nV2嘉泰姆
7.功能概述                        8.相关产品nV2嘉泰姆

一,产品概述(General Description)    nV2嘉泰姆

          The CXSD62126 is a 3A synchronous-rectified Buck converter with integratednV2嘉泰姆
70m Ω power MOSFETs. The CXSD62126, designed with a current-mode controlnV2嘉泰姆
scheme,can convert wide input voltage of 4.3V to 14V to the output voltagenV2嘉泰姆
adjustable from 0.8V to VIN to provide excellent output voltage regulation.nV2嘉泰姆
For high efficiency over all load current range, the CXSD62126 is equippednV2嘉泰姆
with an automatic Skip/PWM mode operation. At light load, the IC operatesnV2嘉泰姆
in the Skip mode, which keeps a constant minimum inductor peak current,nV2嘉泰姆
to reduce switching losses. At heavy load, the IC works in PWM mode, whichnV2嘉泰姆
inductor peak current is programmed by the COMP voltage, to provide highnV2嘉泰姆
efficiency and excel lent output voltage regulation.The CXSD62126 is alsonV2嘉泰姆
equipped with power-on-reset,soft-start, soft-stop, and whole protectionsnV2嘉泰姆
(under-voltage,over-voltage, over-temperature, and current-limit) into anV2嘉泰姆
single package. In shutdown mode, the supply current drops below 3μA.nV2嘉泰姆
This device, available in a 8-pin SOP-8 package, provides a very compactnV2嘉泰姆
system solution with minimal external components and PCB area.nV2嘉泰姆
二.产品特点(Features)nV2嘉泰姆

Wide Input Voltage from 4.3V to 14VnV2嘉泰姆
Output Current up to 3AnV2嘉泰姆
Adjustable Output Voltage from 0.8V to V INnV2嘉泰姆
- ±2% System AccuracynV2嘉泰姆
70mΩ Integrated Power MOSFETsnV2嘉泰姆
High Efficiency up to 95%nV2嘉泰姆
- Automatic Skip/PWM Mode OperationnV2嘉泰姆
Current-Mode OperationnV2嘉泰姆
- Easy Feedback CompensationnV2嘉泰姆
- Stable with Low ESR Output CapacitorsnV2嘉泰姆
- Fast Load/Line Transient ResponsenV2嘉泰姆
Power-On-Reset MonitoringnV2嘉泰姆
Fixed 500kHz Switching Frequency in PWM ModenV2嘉泰姆
Built-In Digital Soft-Start and Soft-StopnV2嘉泰姆
Current-Limit Protection with Frequency FoldbacknV2嘉泰姆
123% Over-Voltage ProtectionnV2嘉泰姆
Hiccup-Mode 50% Under-Voltage ProtectionnV2嘉泰姆
Over-Temperature ProtectionnV2嘉泰姆
<3μA Quiescent Current in Shutdown ModenV2嘉泰姆
Small SOP-8 PackagenV2嘉泰姆
Lead Free and Green Devices AvailablenV2嘉泰姆
(RoHS Compliant)nV2嘉泰姆
三,应用范围 (Applications)nV2嘉泰姆

OLPC, UMPCnV2嘉泰姆
Notebook ComputernV2嘉泰姆
Handheld Portable DevicenV2嘉泰姆
Step-Down Converters Requiring High EfficiencynV2嘉泰姆
and 3A Output CurrentnV2嘉泰姆
四.下载产品资料PDF文档 nV2嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！nV2嘉泰姆

 nV2嘉泰姆

五,产品封装图 (Package)nV2嘉泰姆

nV2嘉泰姆

六.电路原理图nV2嘉泰姆

nV2嘉泰姆

七,功能概述nV2嘉泰姆

Thermal ConsiderationnV2嘉泰姆

In most applications, the JTMA7104A does not dissipate much heat due to its high efficiency. But, in applicationsnV2嘉泰姆
where the JTMA7104A is running at high ambient tem perature with low supply voltage and high duty cycles, thenV2嘉泰姆
heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reachesnV2嘉泰姆
approximately 150°C, both power switches will be turned off and the SW node will become high impedance.nV2嘉泰姆
To avoid the JTMA7104A from exceeding the maximum junction temperature, the user will need to do some ther-nV2嘉泰姆
mal analysis. The goal of the thermal analysis is to deter mine whether the power dissipated exceeds the maxi-nV2嘉泰姆
mum junction temperature of the part. The power dissipated by the part is approximated:nV2嘉泰姆
PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D))nV2嘉泰姆
The temperature rise is given by:nV2嘉泰姆
TR = (PD)(èJA)nV2嘉泰姆
Where PD is the power dissipated by the regulator, D isnV2嘉泰姆
duty cycle of main switchnV2嘉泰姆
D = VOUT/VINnV2嘉泰姆
The èJA is the thermal resistance from the junction of thenV2嘉泰姆
die to the ambient temperature. The junction temperature,nV2嘉泰姆
TJ, is given by:nV2嘉泰姆
TJ = TA + TRnV2嘉泰姆
Where TA is the ambient temperature.
Layout ConsiderationnV2嘉泰姆
For all switching power supplies, the layout is an impor tant step in the design; especially at high peak currentsnV2嘉泰姆
and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and dutynV2嘉泰姆
cycle jitter.nV2嘉泰姆
1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND withnV2嘉泰姆
short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GNDnV2嘉泰姆
to capacitor less than 2mm respectively is recommended.nV2嘉泰姆
2. To minimize copper trace connections that can inject noise into the system, the inductor should be placednV2嘉泰姆
as close as possible to the SW pin to minimize the noise coupling into other circuits.nV2嘉泰姆
3. The output capacitor should be place closed to converter VOUT and GND.nV2嘉泰姆
4. Since the feedback pin and network is a high imped ance circuit the feedback network should be routednV2嘉泰姆
away from the inductor. The feedback pin and feedback network should be shielded with a ground planenV2嘉泰姆
or trace to minimize noise coupling into this circuit.nV2嘉泰姆
5. A star ground connection or ground plane minimizes ground shifts and noise is recommended.nV2嘉泰姆
八,相关产品                  更多同类产品.......nV2嘉泰姆

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