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目录0Qj嘉泰姆

1.产品概述                       2.产品特点0Qj嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 0Qj嘉泰姆
5.产品封装图                     6.电路原理图                   0Qj嘉泰姆
7.功能概述                        8.相关产品0Qj嘉泰姆

一,产品概述(General Description)   0Qj嘉泰姆

       The CXSD6288 is a dual-channel, constant on-time, and 0Qj嘉泰姆
synchronous PWM controller which drives dual N-channel MOSFETs0Qj嘉泰姆
for each channel. The CXSD6288 steps down high voltage of a battery0Qj嘉泰姆
to generate low-voltage chipset or RAM supplies in notebook computers.0Qj嘉泰姆
The CXSD6288 provides excellent transient response and accurate DC voltage output in either PFM or PWM mode. In PFM mode, the CXSD6288 provides very high efficiency over light to heavy loads with loading-modu-0Qj嘉泰姆
lated switching frequencies. The Forced-PWM mode works nearly at constant frequency for low-noise requirements.0Qj嘉泰姆
        The CXSD6288 is equipped with accurate current-limit,output under-voltag, and output over-voltage protections,perfect for NB applications. A Power-On-Reset function monitors the voltage on V CC to prevent wrong opera-tion during power on. A soft-start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop  function actively discharges the output capacitors with controlled reverse inductor current. At the end of the soft-stop, the CXSD6288 forces 0Qj嘉泰姆
LGATE high to prevent over-voltage in shutdown. The CXSD6288 has individual enable controls for each channel. Pulling both EN pin low shuts down the whole chip with low quiescent current close to zero.0Qj嘉泰姆
        The CXSD6288 is available in SSOP-28 and QFN4x4-24 packages.0Qj嘉泰姆
二.产品特点(Features)0Qj嘉泰姆

1.）Adjustable Output Voltage up to 5.5V0Qj嘉泰姆
       - 0.9V Reference Voltage0Qj嘉泰姆
       - ±1% Accuracy Over Temperature0Qj嘉泰姆
2.）Operates from an Input Battery Voltage Range of0Qj嘉泰姆
3.）5V to 24V or from 3.3V/5V System Rail0Qj嘉泰姆
4.）Power-On-Reset Monitoring on VCC Pin0Qj嘉泰姆
     Selectable Forced PWM or Automatic PFM/PWM Mode0Qj嘉泰姆
5.）Constant-On-Time Control Scheme0Qj嘉泰姆
     - Switching Frequency Compensation for PWM Mode0Qj嘉泰姆
     - Constant Switching Frequency (CH1: 345kHz,0Qj嘉泰姆
    CH2: 255KHz) in PWM Mode with DC Output Current0Qj嘉泰姆
6.）Excellent Line and Load Transient Responses0Qj嘉泰姆
7.）Adjustable Soft-Start and Soft-Stop0Qj嘉泰姆
8.）Power-Good Outputs for both Channels0Qj嘉泰姆
9.）Adjustable Current-Limit Protection0Qj嘉泰姆
     - Using Sense Resistor or MOSFET’s RDS(ON)0Qj嘉泰姆
10.）115% Over-Voltage Protection0Qj嘉泰姆
- No Negative Output Voltage Occurred0Qj嘉泰姆
11.）70% Under-Voltage Protection0Qj嘉泰姆
12.）Adaptive Dead-Time Control0Qj嘉泰姆
     - Sensing G-to-S Voltage of Power MOSFETs0Qj嘉泰姆
13.）Shutdown Control for both Channels0Qj嘉泰姆
14.）28-pin SSOP (SSOP-28) and 4mmx4mm 24-lead0Qj嘉泰姆
       QFN (QFN4x4-24) Packages0Qj嘉泰姆
15.）Lead Free and Green Devices Available0Qj嘉泰姆
三,应用范围 (Applications)0Qj嘉泰姆

Note Book Computers0Qj嘉泰姆
      - Chipset/RAM Supplies as low as 0.9V0Qj嘉泰姆
       - 1.8V and 2.5V Supplies0Qj嘉泰姆
   Step-Down Converters Requiring High Efficiency0Qj嘉泰姆
四.下载产品资料PDF文档 0Qj嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！0Qj嘉泰姆

 0Qj嘉泰姆

五,产品封装图 (Package)0Qj嘉泰姆

0Qj嘉泰姆

六.电路原理图0Qj嘉泰姆

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七,功能概述0Qj嘉泰姆

Layout Consideration (Cont.)0Qj嘉泰姆
· Keep the switching nodes (UGATEx, LGATEx, BOOTx,PHASEx, and ISENx) away from sensitive small sig-0Qj嘉泰姆
nal nodes since these nodes are fast moving signals.Therefore, keep traces to these nodes as short as0Qj嘉泰姆
possible and there should be no other weak signal traces in parallel with theses traces on any layer.0Qj嘉泰姆
· The signals going through theses traces have both high dv/dt and high di/dt, with high peak charging and0Qj嘉泰姆
discharging current. The traces from the gate drivers to the MOSFETs (UGATEx and LGATEx) should be short0Qj嘉泰姆
and wide.0Qj嘉泰姆
· Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible.0Qj嘉泰姆
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of0Qj嘉泰姆
the node.0Qj嘉泰姆
· The ISENx trace should be a separate trace, and independently go to the drain terminal of the low-side0Qj嘉泰姆
MOSFET. The current sense resistor should be close to ISENx pin. The loop formed by the bottom MOSFET,0Qj嘉泰姆
output inductor, and output capacitor, should be very small. The source of the bottom MOSFET should tie0Qj嘉泰姆
to the negative side of the output capacitor in order for the ISENx pin to get the voltage drop on the RDS(ON).0Qj嘉泰姆
· Decoupling capacitor, compensation component,the resistor dividers, boot capacitors, and soft-start0Qj嘉泰姆
capacitors should be close their pins. (For example,place the decoupling ceramic capacitor near the drain0Qj嘉泰姆
of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain).0Qj嘉泰姆
· The input capacitor should be near the drain of the high-side MOSFET; the high quality ceramic0Qj嘉泰姆
decoupling capacitor can be put close to the VCC and GND pins; the output capacitor should be near the0Qj嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the low-side MOSFET0Qj嘉泰姆
GND.0Qj嘉泰姆
· The drain of the MOSFETs (VIN and PHASEx nodes) should be a large plane for heat sinking. And0Qj嘉泰姆
PHASEx pin traces are also the return path for UGATEx. Connect these pins to the respective0Qj嘉泰姆
converter’s high-side MOSFET source.0Qj嘉泰姆
The CXSD6288 uses ripple mode control. Build the resistor divider close to the VSENx pin so that the0Qj嘉泰姆
high impedance trace is shorter. The VSENx pin traces can’t be closed to the switching signal traces (UGATEx,0Qj嘉泰姆
LGATEx, BOOTx, PHASEx, and ISENx).0Qj嘉泰姆
The PGNDx trace should be a seperate trace, and inpendently go to the source of the low-side MOSFET.0Qj嘉泰姆
For QFN4x4-24 package only, the thermal pad is the PGND of the dual channels. The sources of the both0Qj嘉泰姆
channels’ low-side MOSFETs should be near the PGND respectively.0Qj嘉泰姆

八,相关产品                       更多同类产品...... 0Qj嘉泰姆

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