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首页 > 产品中心 > 电源管理 > DC降压型芯片 > Buck降压型芯片 >CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式
CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式
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CXSD62116A|B|C允许宽输入电压它可以是一个5~12V的电源电压,也可以是两个不同应用的电源电压。上电复位(POR)电路监测VCC电源电压以防止逻辑控制错误。内置数字软启动电路防止输出电压过冲以及限制输入电流。内线0.6V高精度温度补偿参考电压设计满足低输出电压应用的要求

CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式
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目录fea嘉泰姆

1.产品概述                       2.产品特点fea嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 fea嘉泰姆
5.产品封装图                     6.电路原理图                   fea嘉泰姆
7.功能概述                        8.相关产品fea嘉泰姆

一,产品概述(General Description)         fea嘉泰姆
        The CXSD62116A/B/C is a voltage mode, fixed 300kHz-switching frequency,fea嘉泰姆
and synchronous buck controller. The CXSD62116A/B/C allows wide input voltagefea嘉泰姆
that is either a single 5~12V or two supply voltage(s) for various applications.fea嘉泰姆
A power-on-reset (POR) circuit monitors the VCC supply voltage to preventfea嘉泰姆
wrong logic controls. A built-in digital soft-start circuit prevents the outputfea嘉泰姆
voltages from overshoot as well as limits the input current. An internalfea嘉泰姆
0.6V temperature-compensated reference voltage with high accuracy isfea嘉泰姆
designed to meet the requirement of low output voltage applications.fea嘉泰姆
The CXSD62116A/B/C provides excellent output voltage regulations againstfea嘉泰姆
load current variation.fea嘉泰姆
     The controller’s over-current protection monitors the output currentfea嘉泰姆
by using the voltage drops across the RDS(ON)of low-side MOSFET,fea嘉泰姆
eliminating the need for a current sensing resistor that features highfea嘉泰姆
efficiency and low cost.fea嘉泰姆
     The CXSD62116A/B/C also integrates over-voltage protection (OVP) andfea嘉泰姆
under-voltage protection circuit which moni-tors the FB voltage to preventfea嘉泰姆
the PWM output from over and under voltage.fea嘉泰姆
     The CXSD62116A/B/C is available in a simple SOP-8P package.fea嘉泰姆
二.产品特点(Features)fea嘉泰姆
Wide Operation Supply Voltage from 5V to 12Vfea嘉泰姆
Power-On-Reset Monitoring on VCC fea嘉泰姆
Excellent Reference Voltage Regulationsfea嘉泰姆
- 0.6V Internal Referencefea嘉泰姆
- ±1% Over Temperature Rangefea嘉泰姆
Integrated Soft-Startfea嘉泰姆
Automatic PSM/PWM Modesfea嘉泰姆
Voltage Mode PWM Operation with 90% (Max.) Duty Cyclefea嘉泰姆
Under-Voltage Protectionfea嘉泰姆
Adjustable Over-Current Protection Thresholdfea嘉泰姆
- Sensing the RDS(ON) of Low-Side MOSFETfea嘉泰姆
Over-Voltage Protectionfea嘉泰姆
Under-Voltage Protectionfea嘉泰姆
Simple SOP-8P Packagefea嘉泰姆
Lead Free and Green Devices Availablefea嘉泰姆
(RoHS Compliant)fea嘉泰姆
三,应用范围 (Applications)fea嘉泰姆
Graphic Cardsfea嘉泰姆
DSL, Switch HUBfea嘉泰姆
Wireless Lanfea嘉泰姆
Notebook Computerfea嘉泰姆
Mother Boardfea嘉泰姆
LCD Monitor/TVfea嘉泰姆

四.下载产品资料PDF文档 fea嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持fea嘉泰姆

 QQ截图20160419174301.jpgfea嘉泰姆

五,产品封装图 (Package)fea嘉泰姆
fea嘉泰姆
六.电路原理图fea嘉泰姆

blob.pngfea嘉泰姆
七,功能概述fea嘉泰姆
Layout Considerationfea嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thefea嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike acrossfea嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionfea嘉泰姆
of the PWM MOSFET. Before turn-off, the MOSFET is car rying the full load current. During turn-off, current stopsfea嘉泰姆
flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance offea嘉泰姆
the circuit generates a large voltage spike during the switching interval. In general, using short and wide printedfea嘉泰姆
circuit traces should minimize interconnecting imped-fea嘉泰姆

Layout Consideration (Cont.)fea嘉泰姆
ances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combinedfea嘉泰姆

using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold linesfea嘉泰姆
indicating high current paths; these traces must be short and wide. Components along the bold lines should befea嘉泰姆

placed lose together. Below is a checklist for your layout:fea嘉泰姆

- Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since thesefea嘉泰姆

nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.fea嘉泰姆

- The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide.fea嘉泰姆

- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-fea嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.fea嘉泰姆
- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closefea嘉泰姆
their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET asfea嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).fea嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thefea嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.fea嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.fea嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.Close to ICfea嘉泰姆
Figure 8. Layout Guidelinesfea嘉泰姆

八,相关产品                     更多同类产品...... fea嘉泰姆

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