CXSD6290全桥配置中驱动两个高侧P通道和两个低侧N通道mosfet输出由PWM1和PWM2输入独立控制

目录euc嘉泰姆

1.产品概述                       2.产品特点euc嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 euc嘉泰姆
5.产品封装图                     6.电路原理图                   euc嘉泰姆
7.功能概述                        8.相关产品euc嘉泰姆

一,产品概述(General Description)   euc嘉泰姆

       The CXSD6290 is designed to drive two high-side P-chan-neleuc嘉泰姆
MOSFETs and two low-side N-channel MOSFETs in a full-bridgeeuc嘉泰姆
configuration. The outputs are independently controlled by PWM1euc嘉泰姆
and PWM2 input signals.The other features include VCC power-euc嘉泰姆
on-reset and ther-mal shutdown.euc嘉泰姆
二.产品特点(Features)euc嘉泰姆

1.)Wide Input Voltage Range: 4.5V to 13.2Veuc嘉泰姆
2.)Drives a Full-Bridge Inverter(High-Side P-euc嘉泰姆
3.)Channel MOSFETs and Low-Side N-Channel MOSFETs)euc嘉泰姆
4.)Thermal Shutdown Protectioneuc嘉泰姆
5.)VCC Power-On-Reset SOP-8 Packageeuc嘉泰姆
6.)Lead Free and Green Devices Availableeuc嘉泰姆
三,应用范围 (Applications)euc嘉泰姆

 LCD Monitor and LCD TVeuc嘉泰姆
四.下载产品资料PDF文档 euc嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！euc嘉泰姆

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五,产品封装图 (Package)euc嘉泰姆

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FUNCTIONeuc嘉泰姆
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六.电路原理图euc嘉泰姆

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七,功能概述euc嘉泰姆

Thermal Shutdowneuc嘉泰姆
shutdown circuit will pull PGATE outputs high and NGATE outputs low thus turning high-side and low-sideeuc嘉泰姆
MOSFET off. When the driver cools down below 110ïC after a ther-mal shutdown, it resumes normal operationeuc嘉泰姆
and follows the PWM input signals.euc嘉泰姆
Power-On-Reset (POR)euc嘉泰姆
The CXSD6290 provides the power-on-reset function that keeps the driver disable when the VCC voltageeuc嘉泰姆
is insuffi-cient to driver external MOSFETs reliably. The PGATE out-puts remain high and the NGATE outputseuc嘉泰姆
remain low until the VCC voltage exceeds POR threshold. Once the POR threshold is reached, the conditioneuc嘉泰姆
of gate driver outputs is defined by the PWM signals.euc嘉泰姆
Layout Considerationeuc嘉泰姆
In any high switching frequency application, a correct lay-out is important to ensure proper operation of theeuc嘉泰姆
device.With power devices switching at high frequency, the re-sulting current transient will cause voltageeuc嘉泰姆
spike across the interconnecting impedance and parasitic circuit elements. As an example, consider theeuc嘉泰姆
turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. Duringeuc嘉泰姆
turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode.euc嘉泰姆
Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general,euc嘉泰姆
using short and wide printed circuit traces should minimize interconnecting imped-ances and the magnitude ofeuc嘉泰姆
voltage spike. Below is a checklist for your layout :euc嘉泰姆
- Keep the switching nodes (PGATE, NGATE and the drain of the MOSFETs) away from sensitive small sig-euc嘉泰姆
nal nodes (PWM1, PWM2, MS, and DTC ) since these nodes are fast moving signals. Therefore, keep traceseuc嘉泰姆
to these nodes as short as possible.euc嘉泰姆
- Place the drain of the P-MOSFET and the drain of the N-MOSFET as close as possible to minimize the impedeuc嘉泰姆
ance with wide layout plane between the two pads and reduce the voltage bounce of the node.euc嘉泰姆
- The traces from the gate drivers to the MOSFETs (PGATE and NGATE) should be short and wide.euc嘉泰姆
- The VCC decoupling capacitor (C7), C5, C6, and RDTC should be close to their pins.euc嘉泰姆
- The input capacitor should be near the source of the P-MOSFET.euc嘉泰姆
- The drain of the MOSFETs should be a large plane for heat sinking.euc嘉泰姆
八,相关产品             更多同类产品...... euc嘉泰姆