CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式

目录bYw嘉泰姆

1.产品概述                       2.产品特点bYw嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 bYw嘉泰姆
5.产品封装图                     6.电路原理图                   bYw嘉泰姆
7.功能概述                        8.相关产品bYw嘉泰姆

一,产品概述(General Description)         bYw嘉泰姆
        The CXSD62116A/B/C is a voltage mode, fixed 300kHz-switching frequency,bYw嘉泰姆
and synchronous buck controller. The CXSD62116A/B/C allows wide input voltagebYw嘉泰姆
that is either a single 5~12V or two supply voltage(s) for various applications.bYw嘉泰姆
A power-on-reset (POR) circuit monitors the VCC supply voltage to preventbYw嘉泰姆
wrong logic controls. A built-in digital soft-start circuit prevents the outputbYw嘉泰姆
voltages from overshoot as well as limits the input current. An internalbYw嘉泰姆
0.6V temperature-compensated reference voltage with high accuracy isbYw嘉泰姆
designed to meet the requirement of low output voltage applications.bYw嘉泰姆
The CXSD62116A/B/C provides excellent output voltage regulations againstbYw嘉泰姆
load current variation.bYw嘉泰姆
     The controller’s over-current protection monitors the output currentbYw嘉泰姆
by using the voltage drops across the RDS(ON)of low-side MOSFET,bYw嘉泰姆
eliminating the need for a current sensing resistor that features highbYw嘉泰姆
efficiency and low cost.bYw嘉泰姆
     The CXSD62116A/B/C also integrates over-voltage protection (OVP) andbYw嘉泰姆
under-voltage protection circuit which moni-tors the FB voltage to preventbYw嘉泰姆
the PWM output from over and under voltage.bYw嘉泰姆
     The CXSD62116A/B/C is available in a simple SOP-8P package.bYw嘉泰姆
二.产品特点(Features)bYw嘉泰姆
Wide Operation Supply Voltage from 5V to 12VbYw嘉泰姆
Power-On-Reset Monitoring on VCC bYw嘉泰姆
Excellent Reference Voltage RegulationsbYw嘉泰姆
- 0.6V Internal ReferencebYw嘉泰姆
- ±1% Over Temperature RangebYw嘉泰姆
Integrated Soft-StartbYw嘉泰姆
Automatic PSM/PWM ModesbYw嘉泰姆
Voltage Mode PWM Operation with 90% (Max.) Duty CyclebYw嘉泰姆
Under-Voltage ProtectionbYw嘉泰姆
Adjustable Over-Current Protection ThresholdbYw嘉泰姆
- Sensing the RDS(ON) of Low-Side MOSFETbYw嘉泰姆
Over-Voltage ProtectionbYw嘉泰姆
Under-Voltage ProtectionbYw嘉泰姆
Simple SOP-8P PackagebYw嘉泰姆
Lead Free and Green Devices AvailablebYw嘉泰姆
(RoHS Compliant)bYw嘉泰姆
三,应用范围 (Applications)bYw嘉泰姆
Graphic CardsbYw嘉泰姆
DSL, Switch HUBbYw嘉泰姆
Wireless LanbYw嘉泰姆
Notebook ComputerbYw嘉泰姆
Mother BoardbYw嘉泰姆
LCD Monitor/TVbYw嘉泰姆

四.下载产品资料PDF文档 bYw嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！bYw嘉泰姆

 bYw嘉泰姆

五,产品封装图 (Package)bYw嘉泰姆
bYw嘉泰姆
六.电路原理图bYw嘉泰姆

bYw嘉泰姆
七,功能概述bYw嘉泰姆
Layout ConsiderationbYw嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thebYw嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike acrossbYw嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionbYw嘉泰姆
of the PWM MOSFET. Before turn-off, the MOSFET is car rying the full load current. During turn-off, current stopsbYw嘉泰姆
flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance ofbYw嘉泰姆
the circuit generates a large voltage spike during the switching interval. In general, using short and wide printedbYw嘉泰姆
circuit traces should minimize interconnecting imped-bYw嘉泰姆

Layout Consideration (Cont.)bYw嘉泰姆
ances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combinedbYw嘉泰姆

using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold linesbYw嘉泰姆
indicating high current paths; these traces must be short and wide. Components along the bold lines should bebYw嘉泰姆

placed lose together. Below is a checklist for your layout:bYw嘉泰姆

- Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since thesebYw嘉泰姆

nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.bYw嘉泰姆

- The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide.bYw嘉泰姆

- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-bYw嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.bYw嘉泰姆
- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closebYw嘉泰姆
their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET asbYw嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).bYw嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thebYw嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.bYw嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.bYw嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.Close to ICbYw嘉泰姆
Figure 8. Layout GuidelinesbYw嘉泰姆

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