CXSD62121 VTT的输出电压只需要20μF的陶瓷输出电容就可以稳定和快速的瞬态响应

发布时间:2020-04-24 19:36:40 浏览次数:279 作者:oumao18 来源:嘉泰姆
摘要:CXSD62121在轻载期间,允许下垂功能调整输出电压。LDO设计用于为DDR-SDRAM终端提供双向输出电流的稳压。该装置集成了两个功率晶体管,源或汇电流高达1.5A。它还集成了电流限制和热关机保护。
CXSD62121 VTT的输出电压只需要20μF的陶瓷输出电容就可以稳定和快速的瞬态响应

目录JgC嘉泰姆

1.产品概述                       2.产品特点JgC嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 JgC嘉泰姆
5.产品封装图                     6.电路原理图                   JgC嘉泰姆
7.功能概述                        8.相关产品JgC嘉泰姆

一,产品概述(General Description)  JgC嘉泰姆

    The CXSD62121A CXSD62121B CXSD62121 integrates a synchronous buck PWM con-troller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It offers the lowest total solution cost in system where space is at a premium.  The CXSD62121A CXSD62121B CXSD62121 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode.In Pulse Frequency Mode (PFM), the CXSD62121A CXSD62121B CXSD62121 provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. On TQFN-20 Package,the Forced PWM Mode works nearly at constant frequency for low-noise requirements.  The CXSD62121A CXSD62121B CXSD62121 is equipped with accurate current-limit,output under-voltage, and output over-voltage protections.A Power-On- Reset function monitors the voltage on VCC prevents wrong operation during power on. Droop func-tion is allowed to adjust output voltage during light load period.The LDO is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination.The device integrates two power transistors to source or sink current up to 1.5A. It also incorporates current-limit and thermal shutdown protection.The output voltage of LDO tracks the voltage at VREF pin.An internal resistor divider is used to provide a half volt-age of VREF for VTTREF and VTT Voltage. The VTT output voltage is only requiring 20μF of ceramic output capaci tance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state)and suspend state (S4/S5 state) for device, when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF                                                         JgC嘉泰姆

产品特点(Features)JgC嘉泰姆

High Input Voltages Range from 3V to 28V Input PowerJgC嘉泰姆
Provide Adjustable Output Voltage from 0.75V toJgC嘉泰姆
5.5V +1% Accuracy over TemperatureJgC嘉泰姆
Integrated MOSFET Drivers and Bootstrap Forward P-CH MOSFETJgC嘉泰姆
Low Quiescent Current (200μA)JgC嘉泰姆
Excellent Line and Load Transient ResponsesJgC嘉泰姆
PFM Mode for Increased Light Load EfficiencyJgC嘉泰姆
Constant On-Time Controller SchemeJgC嘉泰姆
- Switching Frequency Compensation for PWM ModeJgC嘉泰姆
- Adjustable Switching Frequency from 100kHz toJgC嘉泰姆
550kHz in PWM Mode with DC Output CurrentJgC嘉泰姆
S3 and S5 Pins Control The Device in S0, S3 or S4/S5 StateJgC嘉泰姆
Power Good MonitoringJgC嘉泰姆
Extra Droop Voltage Control Function withJgC嘉泰姆
Adjustable Current SettingJgC嘉泰姆
70% Under-Voltage Protection (UVP)JgC嘉泰姆
125% Over-Voltage Protection (OVP)JgC嘉泰姆
Adjustable Current-Limit ProtectionJgC嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)JgC嘉泰姆
TQFN-20 3mmx3mm Thin packageJgC嘉泰姆
Lead Free Available (RoHS Compliant)JgC嘉泰姆
+1.5A LDO Section (VTT)JgC嘉泰姆
Sourcing or Sinking Current up to 1.5AJgC嘉泰姆
Fast Transient Response for Output VoltageJgC嘉泰姆
Output Ceramic Capacitors Support at least 10μMLCCJgC嘉泰姆
VTT and VTTREF Track at Half the VDDQSNS by internal dividerJgC嘉泰姆
+20mV Accuracy for VTT and VTTREFJgC嘉泰姆
Independent Over-Current Limit (OCL)JgC嘉泰姆
Thermal Shutdown ProtectionJgC嘉泰姆
三,应用范围 (Applications)JgC嘉泰姆


DDR2, and DDR3 Memory Power SuppliesJgC嘉泰姆
SSTL-2 SSTL-18 and HSTL TerminationJgC嘉泰姆
四.下载产品资料PDF文档 JgC嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持JgC嘉泰姆

 QQ截图20160419174301.jpgJgC嘉泰姆

五,产品封装图 (Package)JgC嘉泰姆


blob.pngJgC嘉泰姆
六.电路原理图JgC嘉泰姆


blob.pngJgC嘉泰姆

七,功能概述JgC嘉泰姆


Soft- Start (cont.)JgC嘉泰姆

During soft-start stage before the PGOOD pin is ready,JgC嘉泰姆
the under voltage protection is prohibited. The over volt-JgC嘉泰姆
age and current limit protection functions are enabled. IfJgC嘉泰姆
the output capacitor has residue voltage before startup,JgC嘉泰姆
both low-side and high-side MOSFETs are in off-stateJgC嘉泰姆
until the internal digital soft start voltage equal the inter-JgC嘉泰姆
nal feedback voltage. This will ensure the output voltageJgC嘉泰姆
starts from its existing voltage level.JgC嘉泰姆
The VTT LDO part monitors the output current, both sourc-JgC嘉泰姆
ing and sinking current, and limits the maximum outputJgC嘉泰姆
current to prevent damages during current overload orJgC嘉泰姆
short circuit (shorted from VTT to GND or VLDOIN)JgC嘉泰姆
conditions.JgC嘉泰姆
The VTT LDO provides a soft-start function, using theJgC嘉泰姆
constant current to charge the output capacitor that givesJgC嘉泰姆
a rapid and linear output voltage rise. If the load current isJgC嘉泰姆
above the current limit start-up, the VTT cannot startJgC嘉泰姆
successfully.CXSD62121A CXSD62121B CXSD62121 has an independent counter for each output,JgC嘉泰姆
but the PGOOD signal indicates only the status of VDDQJgC嘉泰姆
and does not indicate VTT power good externally.JgC嘉泰姆
Power-Good Output (PGOOD)JgC嘉泰姆
PGOOD is an open-drain output and the PGOOD com-JgC嘉泰姆
parator continuously monitors the output voltage. PGOODJgC嘉泰姆
is actively held low in shutdown, and standby. When PWMJgC嘉泰姆
converter’s output voltage is greater than 95% of its tar-JgC嘉泰姆
get value, the internal open-drain device will be pulledJgC嘉泰姆
low. After 63μs debounce time, the PGOOD goes high.JgC嘉泰姆
The PGOOD goes low if VVDDQ output is 10% below orJgC嘉泰姆
above its nominal regulation point.JgC嘉泰姆
Under Voltage ProtectionJgC嘉泰姆
In the process of operation, if a short-circuit occurs, theJgC嘉泰姆
output voltage will drop quickly. When load current is big-JgC嘉泰姆
ger than current limit threshold value, the output voltageJgC嘉泰姆
will fall out of the required regulation range. The under-JgC嘉泰姆
voltage continually monitors the setting output voltageJgC嘉泰姆
after 2ms of PWM operations to ensure startup. If a loadJgC嘉泰姆
step is strong enough to pull the output voltage lowerJgC嘉泰姆
than the under voltage threshold (70% of normal outputJgC嘉泰姆
voltage), CXSD62121A CXSD62121B CXSD62121 shuts down the output gradually andJgC嘉泰姆
latches off both high and low side MOSFETs.JgC嘉泰姆
Over Voltage Protection (OVP)JgC嘉泰姆
The feedback voltage should increase over 125% of theJgC嘉泰姆
reference voltage due to the high-side MOSFET failure orJgC嘉泰姆
for other reasons, and the over voltage protection com-JgC嘉泰姆
parator designed with a 1.5μs noise filter will force theJgC嘉泰姆
low-side MOSFET gate driver to be high. This action ac-JgC嘉泰姆
tively pulls down the output voltage and eventually at-JgC嘉泰姆
tempts to blow the battery fuse.JgC嘉泰姆
When the OVP occurs, the PGOOD pin will pull down andJgC嘉泰姆
latch-off the converter. This OVP scheme only clamps theJgC嘉泰姆
voltage overshoot, and does not invert the output voltageJgC嘉泰姆
when otherwise activated with a continuously high outputJgC嘉泰姆
from low-side MOSFET driver. It’s a common problem forJgC嘉泰姆
OVP schemes with a latch. Once an over-voltage faultJgC嘉泰姆
condition is set, toggling VCC power-on-reset signal canJgC嘉泰姆
only reset it.JgC嘉泰姆
PWM Converter Current LimitJgC嘉泰姆
The current-limit circuit employs a unique “valley” currentJgC嘉泰姆
sensing algorithm (Figure 2). CS pin should be con-JgC嘉泰姆
nected to VCC through the trip voltage-setting resistor,JgC嘉泰姆
RCS. CS terminal sinks 5mA current, ICS, and the currentJgC嘉泰姆
limit threshold is set to the voltage across the RCS. TheJgC嘉泰姆
voltage between or CS_GND pin and PHASE pin moni-JgC嘉泰姆
tors the inductor current so that PHASE pin should beJgC嘉泰姆
connected to the drain terminal of the low side MOSFET.JgC嘉泰姆
PGND is used as the positive current sensing node soJgC嘉泰姆
that PGND should be connected to the proper currentJgC嘉泰姆
sensing device, i.e. the sense resistor or the source ter-JgC嘉泰姆
minal of the low side MOSFET.JgC嘉泰姆
If the magnitude of the current-sense signal is above theJgC嘉泰姆
current-limit threshold, the PWM is not allowed to initiateJgC嘉泰姆
a new cycle. The actual peak current is greater than theJgC嘉泰姆
current-limit threshold by an amount equal to the induc-JgC嘉泰姆
tor ripple current. Therefore, the exact current- limit char-JgC嘉泰姆
acteristic and maximum load capability are a function ofJgC嘉泰姆
the sense resistance, inductor value, and input voltage.JgC嘉泰姆
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