目录
产品概述 返回TOPG3j嘉泰姆
The CXLC8980 consists of 14+1 channel buffers target
toward the needs of thin film transistor liquid crystal
display (TFT LCD). This device incorporates one
Vcom buffer and 14 gamma buffers, and are programmed
through I2
C interface. It contains two register
banks which can store two different sets of gamma
reference values. Each buffer is capable of driving
heavy capacitive loads and offering large current loading
(Vcom: 100mA, Gammas: 25mA).
The CXLC8980 is available in the TQFN5X5-32 package.
产品特点 返回TOPG3j嘉泰姆
„ Supply Operation Range : 6.5V to 18VG3j嘉泰姆
„ 14+1 Channels : G3j嘉泰姆
--- 14 Channel Rail-to-Rail Programmable
Gamma Buffers G3j嘉泰姆
Š 10 bits Resolution for each Channel G3j嘉泰姆
Š 25mA Output Current for each Channel G3j嘉泰姆
Š 2 Banks Registers Using Bank_Sel to Select
which Bank Data Output G3j嘉泰姆
---1 Channel Rail-to-Rail Vcom Buffer: G3j嘉泰姆
Š 7 Bits Adjustable Output G3j嘉泰姆
Š ±100mA Output Current G3j嘉泰姆
Š ±140mA Output Short-Circuit Current G3j嘉泰姆
Š 20V/μs Slew Rate G3j嘉泰姆
„ 2-Wire I2
C Slave Mode InterfaceG3j嘉泰姆
„ Using One Control Pin Enable to Store Data into
Non-Volatile Memory (NVM) G3j嘉泰姆
„ Non-Volatile Memory (NVM) Store Setting
(at Least 100 Re-Write Times) G3j嘉泰姆
„ TQFN5X5-32 PackageG3j嘉泰姆
应用范围 返回TOPG3j嘉泰姆
TFT-LCD Monitors G3j嘉泰姆
„ LCD TelevisionsG3j嘉泰姆
技术规格书（产品PDF) 返回TOP G3j嘉泰姆
需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持</span>！</span>
G3j嘉泰姆
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产品封装图 返回TOPG3j嘉泰姆
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电路原理图 返回TOPG3j嘉泰姆
G3j嘉泰姆
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ntegrated BufferG3j嘉泰姆 |
Part NO.G3j嘉泰姆 | VDDG3j嘉泰姆 (V)G3j嘉泰姆 minG3j嘉泰姆 | VDD G3j嘉泰姆 (V)G3j嘉泰姆 maxG3j嘉泰姆 | CH G3j嘉泰姆 Vr+G3j嘉泰姆 VcomG3j嘉泰姆 | IOUTG3j嘉泰姆 (mA) G3j嘉泰姆 Vr,VcomG3j嘉泰姆 | S/R G3j嘉泰姆 (V/μs）</span>G3j嘉泰姆 Vr,VcomG3j嘉泰姆 | BW (MHz）</span>G3j嘉泰姆 Vr,VcomG3j嘉泰姆 | ISC (mA)G3j嘉泰姆 Vr,VcomG3j嘉泰姆 | NoteG3j嘉泰姆 | PackageG3j嘉泰姆 |
CXLC8973G3j嘉泰姆 | 6.5G3j嘉泰姆 | 18G3j嘉泰姆 | 1G3j嘉泰姆 | 100G3j嘉泰姆 | 20G3j嘉泰姆 | 19G3j嘉泰姆 | 260G3j嘉泰姆 | SMBus, Rail-to-Rail OutputG3j嘉泰姆 | TDFN3X3-10G3j嘉泰姆 |
CXLC8974G3j嘉泰姆 | 9G3j嘉泰姆 | 20G3j嘉泰姆 | 14+1G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 16, 70G3j嘉泰姆 | 10, 19G3j嘉泰姆 | 100, 260G3j嘉泰姆 | Rail-to-Rail Output, G3j嘉泰姆 SMBus,2 Banks MTPG3j嘉泰姆 | QFN5X5-32G3j嘉泰姆 |
CXLC8975G3j嘉泰姆 | 6.5G3j嘉泰姆 | 19.5G3j嘉泰姆 | 18+1G3j嘉泰姆 | 30, 100G3j嘉泰姆 | 16, 80G3j嘉泰姆 | 9, 15G3j嘉泰姆 | 120, 300G3j嘉泰姆 | Rail-to-Rail OutputG3j嘉泰姆 | TQFP7X7-48/(FD)G3j嘉泰姆 |
CXLC8976G3j嘉泰姆 | 6.5G3j嘉泰姆 | 19.5G3j嘉泰姆 | 14+1G3j嘉泰姆 | 30, 100G3j嘉泰姆 | 16, 80G3j嘉泰姆 | 9, 15G3j嘉泰姆 | 120, 300G3j嘉泰姆 | Rail-to-Rail OutputG3j嘉泰姆 | TQFP7X7-48/(FD)G3j嘉泰姆 |
CXLC8977G3j嘉泰姆 | 7G3j嘉泰姆 | 20G3j嘉泰姆 | 12+1G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 16, 50G3j嘉泰姆 | 30G3j嘉泰姆 | 100, 300G3j嘉泰姆 | Rail-to-Rail Output, G3j嘉泰姆 SMBus,2 Banks REGG3j嘉泰姆 | QFN4X4-24G3j嘉泰姆 |
CXLC8978G3j嘉泰姆 | 7G3j嘉泰姆 | 20G3j嘉泰姆 | 16+2G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 16, 50G3j嘉泰姆 | 30G3j嘉泰姆 | 100, 300G3j嘉泰姆 | Rail-to-Rail Output,G3j嘉泰姆 SMBus,2 Banks MTPG3j嘉泰姆 | QFN5X5-28G3j嘉泰姆 |
CXLC8979G3j嘉泰姆 | 7G3j嘉泰姆 | 20G3j嘉泰姆 | 12+1+1G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 16, 50G3j嘉泰姆 | 30G3j嘉泰姆 | 100, 300G3j嘉泰姆 | Rail-to-Rail Output, SMBus,Banks MTP, CRCG3j嘉泰姆 | QFN4X4-24G3j嘉泰姆 |
CXLC8980G3j嘉泰姆 | 6.5G3j嘉泰姆 | 18G3j嘉泰姆 | 14+1G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 20, 20G3j嘉泰姆 | 10, 20G3j嘉泰姆 | 75, 140G3j嘉泰姆 | Rail-to-Rail Output,SMBusG3j嘉泰姆 ,2 Banks MTP, ChecksumG3j嘉泰姆 | TQFN5X5-32G3j嘉泰姆 |
CXLC8981G3j嘉泰姆 | 7G3j嘉泰姆 | 18G3j嘉泰姆 | 1G3j嘉泰姆 | 100G3j嘉泰姆 | 23G3j嘉泰姆 | 20G3j嘉泰姆 | 270G3j嘉泰姆 | SMBus,Rail-to-Rail OutputG3j嘉泰姆 | TDFN3X3-8G3j嘉泰姆 |
CXLC8982G3j嘉泰姆 | 7G3j嘉泰姆 | 18G3j嘉泰姆 | 1G3j嘉泰姆 | 100G3j嘉泰姆 | --G3j嘉泰姆 | --G3j嘉泰姆 | --G3j嘉泰姆 | SMBus, VCOM REFG3j嘉泰姆 | TDFN3X3-8G3j嘉泰姆 |
CXLC8983G3j嘉泰姆 | 7G3j嘉泰姆 | 20G3j嘉泰姆 | 8+1G3j嘉泰姆 | 25, 100G3j嘉泰姆 | 16, 50G3j嘉泰姆 | 30G3j嘉泰姆 | 100, 300G3j嘉泰姆 | SMBus, Rail-to-Rail G3j嘉泰姆 Output,2 Bank MTPG3j嘉泰姆 | QFN4X4-24G3j嘉泰姆 |
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