LPDDR2/LPDDR3 Termination Regulator CXEP3473 is a 3A sink/source tracking termination regulator. It is specifically designed for low-cost/ low-external component count systems

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The CXEP3473 is a 3A sink/source tracking termination regulator. It is specifically designed for low-cost/ low-external component count systems. The CXEP3473 maintains a high speed operational amplifier that provides fast load transient response and only requires 20μF (2×10μF) of ceramic output capacitance. The CXEP3473 supports remote sensing functions and all features required to power the LPDDR2 /LPDDR3 /DDR IIIL VTT bus termination according to the JEDEC specification. In addition, the CXEP3473includes integrated sleep-state controls placing VTT in High-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (Shutdown). The CXEP3473is available in the thermally efficient TDFN2X2-10.

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„ Support 1.2V LPDDR2/LPDDR3 and DDR IIIL (0.675VTT) Requirements „ Input Voltage Range: 3V to 5.5V V6w嘉泰姆

„ VLDOIN Voltage Range: 1.2V to 3.6V V6w嘉泰姆

„ Requires Only 20μF Ceramic Output Capacitance V6w嘉泰姆

 „ Supports High-Z in S3 and Soft-Off in S5 V6w嘉泰姆

„ Integrated Divider Tracks 1/2 VDDQSNS for Both VTT and VTTREF V6w嘉泰姆

„ Remote Sensing (VTTSNS) V6w嘉泰姆

„ ±20mV Accuracy for VTT and VTTREF V6w嘉泰姆

„ 10mA Buffered Reference (VTTREF) V6w嘉泰姆

„ Built-In Soft-Start V6w嘉泰姆

„ Over Current Protection V6w嘉泰姆

„ Thermal Shutdown Protection V6w嘉泰姆

„ TDFN2X2-10 PackageV6w嘉泰姆

   应用范围 返回TOPV6w嘉泰姆

„ DDR IIIL Memory Termination V6w嘉泰姆

„ LPDDR2/LPDDR3 Memory Termination V6w嘉泰姆

„ SSTL−2, SSTL−18 V6w嘉泰姆

„ HSTL TerminationV6w嘉泰姆

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