5A同步降压转换器CXSD62122 50mΩ P沟道功率MOSFET和20mΩ N沟道功率MOSFET电流模式控制方案

发布时间:2020-04-24 19:36:32 浏览次数:286 作者:oumao18 来源:嘉泰姆
摘要:CXSD62122 5A同步降压转换器,集成了50mΩP沟道功率MOSFET和20mΩN沟道功率MOSFET。该器件采用电流模式控制方案,可将4.5~26V输入电压转换为0.8~90%VIN可调的输出电压,提供良好的输出电压调节
5A同步降压转换器CXSD62122 50mΩ P沟道功率MOSFET和20mΩ N沟道功率MOSFET电流模式控制方案

目录7DJ嘉泰姆

1.产品概述                       2.产品特点7DJ嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 7DJ嘉泰姆
5.产品封装图                     6.电路原理图                   7DJ嘉泰姆
7.功能概述                        8.
相关产品7DJ嘉泰姆

一,产品概述(General Description)   7DJ嘉泰姆


  The CXSD62122 is a 5A, synchronous, step-down converter with integrated 50mΩ P-channel power MOSFET and 20mΩ N-channel power MOSFET.The device, with cur-rent-mode control scheme, can convert 4.5~26V input volt-age to the output voltage adjustable from 0.8 to 90% VIN to provide excellent output voltage regulation.7DJ嘉泰姆
  The CXSD62122 regulates the output voltage in an auto-matic PSM/PWM mode operation, depending on the out-put current, for high efficiency operation over light to full load current. The CXSD62122 is also equipped with power-7DJ嘉泰姆
on-reset, soft-start, and whole protections (including over- voltage, under-voltage, over-temperature, and current-limit) in a single package. In shutdown mode, the supply current drops below 5μA.This device, available in 28-pin TQFN5x6 package, pro-vides a very compact system solution with minimal exter-7DJ嘉泰姆
nal components and good thermal conductance.7DJ嘉泰姆
二.产品特点(Features)7DJ嘉泰姆


Wide Input Voltage from 4.5V to 26V7DJ嘉泰姆
Output Current Up to 5A7DJ嘉泰姆
Adjustable Output Voltage from 0.8V to 90%VIN7DJ嘉泰姆
- 0.8V Reference Voltage7DJ嘉泰姆
- ±2.5% System Accuracy7DJ嘉泰姆
Integrated 50m P-Channel Power MOSFET and7DJ嘉泰姆
20m N-Channel Power MOSFET7DJ嘉泰姆
High Efficiency up to 95%7DJ嘉泰姆
Current-Mode Operation7DJ嘉泰姆
- Stable with Ceramic Output Capacitors7DJ嘉泰姆
- Fast Transient Response7DJ嘉泰姆
Power-On-Reset Monitoring7DJ嘉泰姆
Fixed 380kHz Switching Frequency in PWM Mode7DJ嘉泰姆
Automatic Pulse-Skipping Mode (PSM)/PWM7DJ嘉泰姆
Mode Operation7DJ嘉泰姆
Built-in Digital Soft-Start7DJ嘉泰姆
Output Current-Limit Protection with Frequency7DJ嘉泰姆
Foldback7DJ嘉泰姆
·70% Under-Voltage Protection7DJ嘉泰姆
·Over-Temperature Protection7DJ嘉泰姆
·118% Over-Voltage Protection7DJ嘉泰姆
·<5μA Quiescent Current During Shutdown7DJ嘉泰姆
·Thermal-Enhanced TQFN5x6-28 Package7DJ嘉泰姆
·Pb-Free Available as an Option7DJ嘉泰姆
·Lead Free and Green Devices Available7DJ嘉泰姆
(RoHS Compliant)7DJ嘉泰姆
三,应用范围 (Applications)7DJ嘉泰姆


LCD Monitor / TV7DJ嘉泰姆

SetTop Box7DJ嘉泰姆
Portable DVD7DJ嘉泰姆
Wireless LAN7DJ嘉泰姆
ADSL, Switch HUB7DJ嘉泰姆
Notebook Computer7DJ嘉泰姆
Step-Down Converters Requiring High Efficiency7DJ嘉泰姆
and 5A Output Current7DJ嘉泰姆

四.下载产品资料PDF文档 7DJ嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持7DJ嘉泰姆

 QQ截图20160419174301.jpg7DJ嘉泰姆

五,产品封装图 (Package)7DJ嘉泰姆


7DJ嘉泰姆

六.电路原理图7DJ嘉泰姆


blob.png7DJ嘉泰姆

七,功能概述7DJ嘉泰姆


Inductor Value Calculation7DJ嘉泰姆
The operating frequency and inductor selection are inter-related in that higher operating frequencies permit7DJ嘉泰姆

the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense7DJ嘉泰姆

 of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance7DJ嘉泰姆

value has a direct effect on ripple current.Accepting larger values of ripple current allows the use of low7DJ嘉泰姆

 inductances, but results in higher output voltage ripple7DJ嘉泰姆
Layout Consideration7DJ嘉泰姆
In high power switching regulator, a correct layout is im-portant to ensure proper operation of the regulator.7DJ嘉泰姆

In general, interconnecting impedance should be minimized by using short, wide printed circuit traces. Signal7DJ嘉泰姆

 and power grounds are to be kept separating and finally com-bined using ground plane construction or single7DJ嘉泰姆

 point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components7DJ嘉泰姆

 along the bold lines should be placed close together. The following is a checklist for your layout:7DJ嘉泰姆
1. Firstly, to initial the layout by placing the power components. Orient the power circuitry to achieve a clean7DJ嘉泰姆
power flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas.7DJ嘉泰姆
2. In Figure 2, the loops with the same color bold lines conduct high slew rate current. These interconnecting7DJ嘉泰姆
impedances should be minimized by using wide, short printed circuit traces.7DJ嘉泰姆
3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB.7DJ嘉泰姆
Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching7DJ嘉泰姆
noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace.7DJ嘉泰姆
4. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor C2 should be connected7DJ嘉泰姆
as close to the VIN and UGND pins as possible.7DJ嘉泰姆
5. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. The bulk capacitors C8 are also7DJ嘉泰姆
placed near VIN. Use a wide power ground plane to con- nect the C1, C8, and C4 to provide a low impedance7DJ嘉泰姆
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