2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

发布时间:2020-06-08 08:20:13 浏览次数:321 作者:oumao18 来源:嘉泰姆
摘要:CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度
2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

目录s2g嘉泰姆

1.产品概述                       2.产品特点s2g嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 s2g嘉泰姆
5.产品封装图                     6.电路原理图                   s2g嘉泰姆
7.功能概述                        8.相关产品s2g嘉泰姆

一,产品概述(General Description)         s2g嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.s2g嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.s2g嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withs2g嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slews2g嘉泰姆
rate. All inputs and outputs are rail-to-rail.s2g嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).s2g嘉泰姆
二.产品特点(Features)s2g嘉泰姆


· 2.6V to 6.5V Input Supply Range s2g嘉泰姆

· Current-Mode Step-Up Regulator s2g嘉泰姆

 - Fast Transient Response s2g嘉泰姆

 - 1.2MHz Fixed Operating Frequency s2g嘉泰姆

· ±1.5% High-Accuracy Output Voltage s2g嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET s2g嘉泰姆

· High Efficiency s2g嘉泰姆

· Low Quiescent Current (0.6mA Typical) s2g嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF s2g嘉泰姆

· High-performance Operational Amplifiers s2g嘉泰姆

 - ±150mA Output Short-Circuit Currents2g嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth s2g嘉泰姆

 - Rail-to-Rail Inputs/Outputs s2g嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs s2g嘉泰姆

· Over-Temperature Protection s2g嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) s2g嘉泰姆

· Lead Free Available (RoHS Compliant)s2g嘉泰姆

三,应用范围 (Applications)s2g嘉泰姆


    TFT LCD Displays for Monitorss2g嘉泰姆
   TFT LCD Displays for Notebook Computerss2g嘉泰姆
   Automotive Displayss2g嘉泰姆
四.下载产品资料PDF文档 s2g嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持s2g嘉泰姆

 QQ截图20160419174301.jpgs2g嘉泰姆

五,产品封装图 (Package)s2g嘉泰姆


blob.pngs2g嘉泰姆
blob.pngPin Function Descriptions2g嘉泰姆

Pins2g嘉泰姆

Names2g嘉泰姆

Function Descriptions2g嘉泰姆

CXSU63137s2g嘉泰姆

CXSU63137-1s2g嘉泰姆

CXSU63137-2s2g嘉泰姆

1s2g嘉泰姆

SRCs2g嘉泰姆

SRCs2g嘉泰姆

SRCs2g嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. Bypasss2g嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.s2g嘉泰姆

2s2g嘉泰姆

REFs2g嘉泰姆

REFs2g嘉泰姆

REFs2g嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofs2g嘉泰姆
0.22μFcapacitor closed to the pins.s2g嘉泰姆

3s2g嘉泰姆

AGNDs2g嘉泰姆

AGNDs2g嘉泰姆

AGNDs2g嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect tos2g嘉泰姆
power ground (PGND) underneath the IC.s2g嘉泰姆

4s2g嘉泰姆

PGNDs2g嘉泰姆

PGNDs2g嘉泰姆

PGNDs2g嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-ups2g嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputs2g嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog grounds2g嘉泰姆
(AGND) underneath the IC.s2g嘉泰姆

5s2g嘉泰姆

OUT1s2g嘉泰姆

OUT1s2g嘉泰姆

OUT1s2g嘉泰姆

Output of Operational-Amplifier 1s2g嘉泰姆

6s2g嘉泰姆

NEG1s2g嘉泰姆

NEG1s2g嘉泰姆

NEG1s2g嘉泰姆

Inverting Input of Operational-Amplifier 1s2g嘉泰姆

7s2g嘉泰姆

POS1s2g嘉泰姆

POS1s2g嘉泰姆

POS1s2g嘉泰姆

Non-inverting Input of Operational-Amplifier 1s2g嘉泰姆

8s2g嘉泰姆

NCs2g嘉泰姆

OUT2s2g嘉泰姆

OUT2s2g嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internals2g嘉泰姆
connected of CXSU63137.s2g嘉泰姆

9s2g嘉泰姆

NCs2g嘉泰姆

NEG2s2g嘉泰姆

NEG2s2g嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internals2g嘉泰姆
connected of CXSU63137.s2g嘉泰姆

10s2g嘉泰姆

ICs2g嘉泰姆

POS2s2g嘉泰姆

POS2s2g嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. Internals2g嘉泰姆
connected to GND of CXSU63137s2g嘉泰姆

11s2g嘉泰姆

BGNDs2g嘉泰姆

BGNDs2g嘉泰姆

BGNDs2g嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)s2g嘉泰姆
underneath the IC.s2g嘉泰姆

12s2g嘉泰姆

NCs2g嘉泰姆

NCs2g嘉泰姆

POS3s2g嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internals2g嘉泰姆
connected of CXSU63137/CXSU63137.s2g嘉泰姆

13s2g嘉泰姆

NCs2g嘉泰姆

NCs2g嘉泰姆

OUT3s2g嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.s2g嘉泰姆

14s2g嘉泰姆

SUPs2g嘉泰姆

SUPs2g嘉泰姆

SUPs2g嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. Bypasss2g嘉泰姆
SUP to BGND with a 0.1μF capacitor.s2g嘉泰姆

15s2g嘉泰姆

NCs2g嘉泰姆

POS3s2g嘉泰姆

POS4s2g嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertings2g嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.s2g嘉泰姆

16s2g嘉泰姆

NCs2g嘉泰姆

NEG3s2g嘉泰姆

NEG4s2g嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofs2g嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.s2g嘉泰姆

17s2g嘉泰姆

NCs2g嘉泰姆

OUT3s2g嘉泰姆

OUT4s2g嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofs2g嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.s2g嘉泰姆

18s2g嘉泰姆

ICs2g嘉泰姆

ICs2g嘉泰姆

POS5s2g嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connecteds2g嘉泰姆
to GND of CXSU63137/CXSU63137.s2g嘉泰姆

19s2g嘉泰姆

NCs2g嘉泰姆

NCs2g嘉泰姆

NEG5s2g嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connecteds2g嘉泰姆
of CXSU63137/CXSU63137.s2g嘉泰姆

20s2g嘉泰姆

NCs2g嘉泰姆

NCs2g嘉泰姆

OUT5s2g嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.s2g嘉泰姆

21s2g嘉泰姆

LXs2g嘉泰姆

LXs2g嘉泰姆

LXs2g嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductors2g嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.s2g嘉泰姆

22s2g嘉泰姆

INs2g嘉泰姆

INs2g嘉泰姆

INs2g嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can ranges2g嘉泰姆
from 2.6V to 6.5V.s2g嘉泰姆

23s2g嘉泰姆

FBs2g嘉泰姆

FBs2g嘉泰姆

FBs2g嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider froms2g嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withins2g嘉泰姆
5mm of FB.s2g嘉泰姆

24s2g嘉泰姆

COMPs2g嘉泰姆

COMPs2g嘉泰姆

COMPs2g嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCs2g嘉泰姆
from COMP to AGND.s2g嘉泰姆

PinFunction Descriptions2g嘉泰姆

Pins2g嘉泰姆

Names2g嘉泰姆

Function Descriptions2g嘉泰姆

CXSU63137s2g嘉泰姆

CXSU63137-1s2g嘉泰姆

CXSU63137-2s2g嘉泰姆

24s2g嘉泰姆

COMPs2g嘉泰姆

COMPs2g嘉泰姆

COMPs2g嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCs2g嘉泰姆
from COMP to AGND.s2g嘉泰姆

25s2g嘉泰姆

FBPs2g嘉泰姆

FBPs2g嘉泰姆

FBPs2g嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of as2g嘉泰姆
resistive voltage-divider between the regulator output and AGND to set thes2g嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-dividers2g嘉泰姆
close to the pin.s2g嘉泰姆

26s2g嘉泰姆

DRVPs2g嘉泰姆

DRVPs2g嘉泰姆

DRVPs2g嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channels2g嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.s2g嘉泰姆

27s2g嘉泰姆

FBNs2g嘉泰姆

FBNs2g嘉泰姆

FBNs2g嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of as2g嘉泰姆
resistive voltage-divider between the regulator output and REF to set thes2g嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-dividers2g嘉泰姆
close to the pin.s2g嘉泰姆

28s2g嘉泰姆

DRVNs2g嘉泰姆

DRVNs2g嘉泰姆

DRVNs2g嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channels2g嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.s2g嘉泰姆

29s2g嘉泰姆

DELs2g嘉泰姆

DELs2g嘉泰姆

DELs2g嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND tos2g嘉泰姆
set the high-voltage switch startup delay.s2g嘉泰姆

30s2g嘉泰姆

CTLs2g嘉泰姆

CTLs2g嘉泰姆

CTLs2g嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchs2g嘉泰姆
between COM and SRC is on and the high-voltage switch between COM ands2g嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRCs2g嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL iss2g嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thans2g嘉泰姆
1.25V.s2g嘉泰姆

31s2g嘉泰姆

DRNs2g嘉泰姆

DRNs2g嘉泰姆

DRNs2g嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channels2g嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceeds2g嘉泰姆
VSRC.s2g嘉泰姆

32s2g嘉泰姆

COMs2g嘉泰姆

COMs2g嘉泰姆

COMs2g嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow thes2g嘉泰姆
voltage on COM to exceed VSRC.s2g嘉泰姆

六.电路原理图s2g嘉泰姆
七,功能概述s2g嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:s2g嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.s2g嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.s2g嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.s2g嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.s2g嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.s2g嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.s2g嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-ups2g嘉泰姆
八,相关产品s2g嘉泰姆

Switching Regulator > Boost Converters2g嘉泰姆

 Part_No s2g嘉泰姆

Packages2g嘉泰姆

Archi-tecture s2g嘉泰姆

Input s2g嘉泰姆

Voltage    s2g嘉泰姆

Max Adj.s2g嘉泰姆

Output s2g嘉泰姆

Voltage s2g嘉泰姆

Switch Current Limit (max) s2g嘉泰姆

Fixed s2g嘉泰姆

Output s2g嘉泰姆

Voltage  s2g嘉泰姆

Switching s2g嘉泰姆

Frequency s2g嘉泰姆

Internal Power   Switch s2g嘉泰姆

Sync. Rectifier s2g嘉泰姆

 

mins2g嘉泰姆

maxs2g嘉泰姆

mins2g嘉泰姆

maxs2g嘉泰姆

(A)s2g嘉泰姆

(V)s2g嘉泰姆

(kHz)s2g嘉泰姆

 

CXSU63133s2g嘉泰姆

SOT89s2g嘉泰姆

VM s2g嘉泰姆

0.9s2g嘉泰姆

5.5s2g嘉泰姆

2.5s2g嘉泰姆

5.5s2g嘉泰姆

0.5s2g嘉泰姆

1.8|2.6|2.8|3s2g嘉泰姆

|3.3|3.8|4.5|5s2g嘉泰姆

-s2g嘉泰姆

Nos2g嘉泰姆

Yess2g嘉泰姆

CXSU63134s2g嘉泰姆

MSOP8|TSSOP8s2g嘉泰姆

|SOP8s2g嘉泰姆

VMs2g嘉泰姆

2.5s2g嘉泰姆

5.5s2g嘉泰姆

2.5s2g嘉泰姆

-s2g嘉泰姆

-s2g嘉泰姆

-s2g嘉泰姆

200 ~ 1000s2g嘉泰姆

Nos2g嘉泰姆

Nos2g嘉泰姆

CXSU63135s2g嘉泰姆

TSSOP8|SOP-8Ps2g嘉泰姆

VMs2g嘉泰姆

1s2g嘉泰姆

5.5s2g嘉泰姆

2.5s2g嘉泰姆

5s2g嘉泰姆

1s2g嘉泰姆

2.5|3.3s2g嘉泰姆

300s2g嘉泰姆

Yess2g嘉泰姆

Yess2g嘉泰姆

CXSU63136s2g嘉泰姆

SOP8s2g嘉泰姆

CMs2g嘉泰姆

3s2g嘉泰姆

40s2g嘉泰姆

1.25s2g嘉泰姆

40s2g嘉泰姆

1.5s2g嘉泰姆

-s2g嘉泰姆

33 ~ 100s2g嘉泰姆

Yess2g嘉泰姆

Nos2g嘉泰姆

CXSU63137s2g嘉泰姆

TQFN5x5-32s2g嘉泰姆

CMs2g嘉泰姆

2.5s2g嘉泰姆

6.5s2g嘉泰姆

2.5s2g嘉泰姆

18s2g嘉泰姆

3s2g嘉泰姆

Nos2g嘉泰姆

1200s2g嘉泰姆

Yess2g嘉泰姆

Nos2g嘉泰姆

CXSU63138s2g嘉泰姆

TSOT23-5s2g嘉泰姆

TDFN2x2-6s2g嘉泰姆

CMs2g嘉泰姆

2.5s2g嘉泰姆

6s2g嘉泰姆

2.5s2g嘉泰姆

20s2g嘉泰姆

2s2g嘉泰姆

-s2g嘉泰姆

1500s2g嘉泰姆

Yess2g嘉泰姆

Nos2g嘉泰姆

CXSU63139s2g嘉泰姆

TQFN4x4-6s2g嘉泰姆

TDFN3x3-12s2g嘉泰姆

CMs2g嘉泰姆

1.8s2g嘉泰姆

5.5s2g嘉泰姆

2.7s2g嘉泰姆

5.5s2g嘉泰姆

5s2g嘉泰姆

-s2g嘉泰姆

1.2s2g嘉泰姆

Yess2g嘉泰姆

Yess2g嘉泰姆

CXSU63140s2g嘉泰姆

SOT23-5s2g嘉泰姆

CMs2g嘉泰姆

2.5s2g嘉泰姆

6s2g嘉泰姆

2.5s2g嘉泰姆

32s2g嘉泰姆

1s2g嘉泰姆

-s2g嘉泰姆

1000s2g嘉泰姆

Yess2g嘉泰姆

Nos2g嘉泰姆

CXSU63141s2g嘉泰姆

TSOT-23-6 s2g嘉泰姆

TDFN2x2-8s2g嘉泰姆

CMs2g嘉泰姆

1.2s2g嘉泰姆

5.5s2g嘉泰姆

1.8s2g嘉泰姆

5.5s2g嘉泰姆

1.2s2g嘉泰姆

-s2g嘉泰姆

1.2s2g嘉泰姆

Yess2g嘉泰姆

Yess2g嘉泰姆

 s2g嘉泰姆

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