2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

发布时间:2020-06-08 08:20:13 浏览次数:305 作者:oumao18 来源:嘉泰姆
摘要:CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度
2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

目录0Kn嘉泰姆

1.产品概述                       2.产品特点0Kn嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 0Kn嘉泰姆
5.产品封装图                     6.电路原理图                   0Kn嘉泰姆
7.功能概述                        8.相关产品0Kn嘉泰姆

一,产品概述(General Description)         0Kn嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.0Kn嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.0Kn嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, with0Kn嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slew0Kn嘉泰姆
rate. All inputs and outputs are rail-to-rail.0Kn嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).0Kn嘉泰姆
二.产品特点(Features)0Kn嘉泰姆


· 2.6V to 6.5V Input Supply Range 0Kn嘉泰姆

· Current-Mode Step-Up Regulator 0Kn嘉泰姆

 - Fast Transient Response 0Kn嘉泰姆

 - 1.2MHz Fixed Operating Frequency 0Kn嘉泰姆

· ±1.5% High-Accuracy Output Voltage 0Kn嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET 0Kn嘉泰姆

· High Efficiency 0Kn嘉泰姆

· Low Quiescent Current (0.6mA Typical) 0Kn嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF 0Kn嘉泰姆

· High-performance Operational Amplifiers 0Kn嘉泰姆

 - ±150mA Output Short-Circuit Current0Kn嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth 0Kn嘉泰姆

 - Rail-to-Rail Inputs/Outputs 0Kn嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs 0Kn嘉泰姆

· Over-Temperature Protection 0Kn嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) 0Kn嘉泰姆

· Lead Free Available (RoHS Compliant)0Kn嘉泰姆

三,应用范围 (Applications)0Kn嘉泰姆


    TFT LCD Displays for Monitors0Kn嘉泰姆
   TFT LCD Displays for Notebook Computers0Kn嘉泰姆
   Automotive Displays0Kn嘉泰姆
四.下载产品资料PDF文档 0Kn嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持0Kn嘉泰姆

 QQ截图20160419174301.jpg0Kn嘉泰姆

五,产品封装图 (Package)0Kn嘉泰姆


blob.png0Kn嘉泰姆
blob.pngPin Function Description0Kn嘉泰姆

Pin0Kn嘉泰姆

Name0Kn嘉泰姆

Function Description0Kn嘉泰姆

CXSU631370Kn嘉泰姆

CXSU63137-10Kn嘉泰姆

CXSU63137-20Kn嘉泰姆

10Kn嘉泰姆

SRC0Kn嘉泰姆

SRC0Kn嘉泰姆

SRC0Kn嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. Bypass0Kn嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.0Kn嘉泰姆

20Kn嘉泰姆

REF0Kn嘉泰姆

REF0Kn嘉泰姆

REF0Kn嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum of0Kn嘉泰姆
0.22μFcapacitor closed to the pins.0Kn嘉泰姆

30Kn嘉泰姆

AGND0Kn嘉泰姆

AGND0Kn嘉泰姆

AGND0Kn嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect to0Kn嘉泰姆
power ground (PGND) underneath the IC.0Kn嘉泰姆

40Kn嘉泰姆

PGND0Kn嘉泰姆

PGND0Kn嘉泰姆

PGND0Kn嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-up0Kn嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of output0Kn嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog ground0Kn嘉泰姆
(AGND) underneath the IC.0Kn嘉泰姆

50Kn嘉泰姆

OUT10Kn嘉泰姆

OUT10Kn嘉泰姆

OUT10Kn嘉泰姆

Output of Operational-Amplifier 10Kn嘉泰姆

60Kn嘉泰姆

NEG10Kn嘉泰姆

NEG10Kn嘉泰姆

NEG10Kn嘉泰姆

Inverting Input of Operational-Amplifier 10Kn嘉泰姆

70Kn嘉泰姆

POS10Kn嘉泰姆

POS10Kn嘉泰姆

POS10Kn嘉泰姆

Non-inverting Input of Operational-Amplifier 10Kn嘉泰姆

80Kn嘉泰姆

NC0Kn嘉泰姆

OUT20Kn嘉泰姆

OUT20Kn嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internal0Kn嘉泰姆
connected of CXSU63137.0Kn嘉泰姆

90Kn嘉泰姆

NC0Kn嘉泰姆

NEG20Kn嘉泰姆

NEG20Kn嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internal0Kn嘉泰姆
connected of CXSU63137.0Kn嘉泰姆

100Kn嘉泰姆

IC0Kn嘉泰姆

POS20Kn嘉泰姆

POS20Kn嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. Internal0Kn嘉泰姆
connected to GND of CXSU631370Kn嘉泰姆

110Kn嘉泰姆

BGND0Kn嘉泰姆

BGND0Kn嘉泰姆

BGND0Kn嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)0Kn嘉泰姆
underneath the IC.0Kn嘉泰姆

120Kn嘉泰姆

NC0Kn嘉泰姆

NC0Kn嘉泰姆

POS30Kn嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internal0Kn嘉泰姆
connected of CXSU63137/CXSU63137.0Kn嘉泰姆

130Kn嘉泰姆

NC0Kn嘉泰姆

NC0Kn嘉泰姆

OUT30Kn嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.0Kn嘉泰姆

140Kn嘉泰姆

SUP0Kn嘉泰姆

SUP0Kn嘉泰姆

SUP0Kn嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. Bypass0Kn嘉泰姆
SUP to BGND with a 0.1μF capacitor.0Kn嘉泰姆

150Kn嘉泰姆

NC0Kn嘉泰姆

POS30Kn嘉泰姆

POS40Kn嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-inverting0Kn嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.0Kn嘉泰姆

160Kn嘉泰姆

NC0Kn嘉泰姆

NEG30Kn嘉泰姆

NEG40Kn嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input of0Kn嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.0Kn嘉泰姆

170Kn嘉泰姆

NC0Kn嘉泰姆

OUT30Kn嘉泰姆

OUT40Kn嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output of0Kn嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.0Kn嘉泰姆

180Kn嘉泰姆

IC0Kn嘉泰姆

IC0Kn嘉泰姆

POS50Kn嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connected0Kn嘉泰姆
to GND of CXSU63137/CXSU63137.0Kn嘉泰姆

190Kn嘉泰姆

NC0Kn嘉泰姆

NC0Kn嘉泰姆

NEG50Kn嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connected0Kn嘉泰姆
of CXSU63137/CXSU63137.0Kn嘉泰姆

200Kn嘉泰姆

NC0Kn嘉泰姆

NC0Kn嘉泰姆

OUT50Kn嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.0Kn嘉泰姆

210Kn嘉泰姆

LX0Kn嘉泰姆

LX0Kn嘉泰姆

LX0Kn嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductor0Kn嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.0Kn嘉泰姆

220Kn嘉泰姆

IN0Kn嘉泰姆

IN0Kn嘉泰姆

IN0Kn嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can range0Kn嘉泰姆
from 2.6V to 6.5V.0Kn嘉泰姆

230Kn嘉泰姆

FB0Kn嘉泰姆

FB0Kn嘉泰姆

FB0Kn嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider from0Kn嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider within0Kn嘉泰姆
5mm of FB.0Kn嘉泰姆

240Kn嘉泰姆

COMP0Kn嘉泰姆

COMP0Kn嘉泰姆

COMP0Kn嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC0Kn嘉泰姆
from COMP to AGND.0Kn嘉泰姆

PinFunction Description0Kn嘉泰姆

Pin0Kn嘉泰姆

Name0Kn嘉泰姆

Function Description0Kn嘉泰姆

CXSU631370Kn嘉泰姆

CXSU63137-10Kn嘉泰姆

CXSU63137-20Kn嘉泰姆

240Kn嘉泰姆

COMP0Kn嘉泰姆

COMP0Kn嘉泰姆

COMP0Kn嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC0Kn嘉泰姆
from COMP to AGND.0Kn嘉泰姆

250Kn嘉泰姆

FBP0Kn嘉泰姆

FBP0Kn嘉泰姆

FBP0Kn嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of a0Kn嘉泰姆
resistive voltage-divider between the regulator output and AGND to set the0Kn嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-divider0Kn嘉泰姆
close to the pin.0Kn嘉泰姆

260Kn嘉泰姆

DRVP0Kn嘉泰姆

DRVP0Kn嘉泰姆

DRVP0Kn嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel0Kn嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.0Kn嘉泰姆

270Kn嘉泰姆

FBN0Kn嘉泰姆

FBN0Kn嘉泰姆

FBN0Kn嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of a0Kn嘉泰姆
resistive voltage-divider between the regulator output and REF to set the0Kn嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-divider0Kn嘉泰姆
close to the pin.0Kn嘉泰姆

280Kn嘉泰姆

DRVN0Kn嘉泰姆

DRVN0Kn嘉泰姆

DRVN0Kn嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel0Kn嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.0Kn嘉泰姆

290Kn嘉泰姆

DEL0Kn嘉泰姆

DEL0Kn嘉泰姆

DEL0Kn嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to0Kn嘉泰姆
set the high-voltage switch startup delay.0Kn嘉泰姆

300Kn嘉泰姆

CTL0Kn嘉泰姆

CTL0Kn嘉泰姆

CTL0Kn嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switch0Kn嘉泰姆
between COM and SRC is on and the high-voltage switch between COM and0Kn嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRC0Kn嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL is0Kn嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less than0Kn嘉泰姆
1.25V.0Kn嘉泰姆

310Kn嘉泰姆

DRN0Kn嘉泰姆

DRN0Kn嘉泰姆

DRN0Kn嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channel0Kn嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceed0Kn嘉泰姆
VSRC.0Kn嘉泰姆

320Kn嘉泰姆

COM0Kn嘉泰姆

COM0Kn嘉泰姆

COM0Kn嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the0Kn嘉泰姆
voltage on COM to exceed VSRC.0Kn嘉泰姆

六.电路原理图0Kn嘉泰姆
七,功能概述0Kn嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:0Kn嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.0Kn嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.0Kn嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.0Kn嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.0Kn嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.0Kn嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.0Kn嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-up0Kn嘉泰姆
八,相关产品0Kn嘉泰姆

Switching Regulator > Boost Converter0Kn嘉泰姆

 Part_No 0Kn嘉泰姆

Package0Kn嘉泰姆

Archi-tecture 0Kn嘉泰姆

Input 0Kn嘉泰姆

Voltage    0Kn嘉泰姆

Max Adj.0Kn嘉泰姆

Output 0Kn嘉泰姆

Voltage 0Kn嘉泰姆

Switch Current Limit (max) 0Kn嘉泰姆

Fixed 0Kn嘉泰姆

Output 0Kn嘉泰姆

Voltage  0Kn嘉泰姆

Switching 0Kn嘉泰姆

Frequency 0Kn嘉泰姆

Internal Power   Switch 0Kn嘉泰姆

Sync. Rectifier 0Kn嘉泰姆

 

min0Kn嘉泰姆

max0Kn嘉泰姆

min0Kn嘉泰姆

max0Kn嘉泰姆

(A)0Kn嘉泰姆

(V)0Kn嘉泰姆

(kHz)0Kn嘉泰姆

 

CXSU631330Kn嘉泰姆

SOT890Kn嘉泰姆

VM 0Kn嘉泰姆

0.90Kn嘉泰姆

5.50Kn嘉泰姆

2.50Kn嘉泰姆

5.50Kn嘉泰姆

0.50Kn嘉泰姆

1.8|2.6|2.8|30Kn嘉泰姆

|3.3|3.8|4.5|50Kn嘉泰姆

-0Kn嘉泰姆

No0Kn嘉泰姆

Yes0Kn嘉泰姆

CXSU631340Kn嘉泰姆

MSOP8|TSSOP80Kn嘉泰姆

|SOP80Kn嘉泰姆

VM0Kn嘉泰姆

2.50Kn嘉泰姆

5.50Kn嘉泰姆

2.50Kn嘉泰姆

-0Kn嘉泰姆

-0Kn嘉泰姆

-0Kn嘉泰姆

200 ~ 10000Kn嘉泰姆

No0Kn嘉泰姆

No0Kn嘉泰姆

CXSU631350Kn嘉泰姆

TSSOP8|SOP-8P0Kn嘉泰姆

VM0Kn嘉泰姆

10Kn嘉泰姆

5.50Kn嘉泰姆

2.50Kn嘉泰姆

50Kn嘉泰姆

10Kn嘉泰姆

2.5|3.30Kn嘉泰姆

3000Kn嘉泰姆

Yes0Kn嘉泰姆

Yes0Kn嘉泰姆

CXSU631360Kn嘉泰姆

SOP80Kn嘉泰姆

CM0Kn嘉泰姆

30Kn嘉泰姆

400Kn嘉泰姆

1.250Kn嘉泰姆

400Kn嘉泰姆

1.50Kn嘉泰姆

-0Kn嘉泰姆

33 ~ 1000Kn嘉泰姆

Yes0Kn嘉泰姆

No0Kn嘉泰姆

CXSU631370Kn嘉泰姆

TQFN5x5-320Kn嘉泰姆

CM0Kn嘉泰姆

2.50Kn嘉泰姆

6.50Kn嘉泰姆

2.50Kn嘉泰姆

180Kn嘉泰姆

30Kn嘉泰姆

No0Kn嘉泰姆

12000Kn嘉泰姆

Yes0Kn嘉泰姆

No0Kn嘉泰姆

CXSU631380Kn嘉泰姆

TSOT23-50Kn嘉泰姆

TDFN2x2-60Kn嘉泰姆

CM0Kn嘉泰姆

2.50Kn嘉泰姆

60Kn嘉泰姆

2.50Kn嘉泰姆

200Kn嘉泰姆

20Kn嘉泰姆

-0Kn嘉泰姆

15000Kn嘉泰姆

Yes0Kn嘉泰姆

No0Kn嘉泰姆

CXSU631390Kn嘉泰姆

TQFN4x4-60Kn嘉泰姆

TDFN3x3-120Kn嘉泰姆

CM0Kn嘉泰姆

1.80Kn嘉泰姆

5.50Kn嘉泰姆

2.70Kn嘉泰姆

5.50Kn嘉泰姆

50Kn嘉泰姆

-0Kn嘉泰姆

1.20Kn嘉泰姆

Yes0Kn嘉泰姆

Yes0Kn嘉泰姆

CXSU631400Kn嘉泰姆

SOT23-50Kn嘉泰姆

CM0Kn嘉泰姆

2.50Kn嘉泰姆

60Kn嘉泰姆

2.50Kn嘉泰姆

320Kn嘉泰姆

10Kn嘉泰姆

-0Kn嘉泰姆

10000Kn嘉泰姆

Yes0Kn嘉泰姆

No0Kn嘉泰姆

CXSU631410Kn嘉泰姆

TSOT-23-6 0Kn嘉泰姆

TDFN2x2-80Kn嘉泰姆

CM0Kn嘉泰姆

1.20Kn嘉泰姆

5.50Kn嘉泰姆

1.80Kn嘉泰姆

5.50Kn嘉泰姆

1.20Kn嘉泰姆

-0Kn嘉泰姆

1.20Kn嘉泰姆

Yes0Kn嘉泰姆

Yes0Kn嘉泰姆

 0Kn嘉泰姆

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